34 search results - page 1 / 7 » 3D floorplanning with thermal vias |
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
Abstract— 3D circuits have the potential to improve performance over traditional 2D circuits by reducing wirelength and interconnect delay. One major problem with 3D circuits is ...
ASPDAC
2010
ACM
13 years 3 months ago
2010
ACM
In this paper, we present a novel algorithm for 3D floorplanning with fixed outline constraints and a particular emphasis on thermal awareness. A computationally efficient thermal ...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
- Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area, and power dissipation in nanometer technologies, its impact...
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
As the technology progresses, interconnect delays have become bottlenecks of chip performance. Three dimensional (3D) integrated circuits are proposed as one way to address this p...
ICCD
2007
IEEE
14 years 1 months ago
2007
IEEE
Most previous 3D IC research focused on “stacking” traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose tech...