4 search results - page 1 / 1 » 3D module placement for congestion and power noise reduction |
GLVLSI
2005
IEEE
13 years 10 months ago
2005
IEEE
3D packaging via System-On-Package (SOP) is a viable alternative to System-On-Chip (SOC) to meet the rigorous requirements of today’s mixed signal system integration. In this wo...
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
— The recent popularity of 3D IC technology stems from its enhanced performance capabilities and reduced wirelength. However, wire congestion and thermal issues are exacerbated d...
JETC
2008
13 years 3 months ago
2008
With aggressive reductions in feature sizes and the integration of multiple functionalities on the same die, bottlenecks due to I/O pin limitations have become a severe issue in to...
DAC
2008
ACM
14 years 5 months ago
2008
ACM
In the design of complex power distribution networks (PDN) with multiple power islands, it is required that the PDN represents a low impedance as seen by the digital modules. This...