10 search results - page 1 / 2 » A 1.2GHz delayed clock generator for high-speed microprocess... |
7
Voted
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...
VTS
2000
IEEE
13 years 9 months ago
2000
IEEE
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable thro...
NETWORKING
2007
13 years 6 months ago
2007
We re-examine the two reasons for the conservative 1-second Minimum TCP-RTO to protect against spurious timeouts: i) the OS clock granularity and ii) the Delayed ACKs. We find tha...
ICCAD
2003
IEEE
13 years 10 months ago
2003
IEEE
Domino circuits have been used in most modern high-performance microprocessor designs because of their high speed, low transistor-count and hazard-free operation. However, with te...