11 search results - page 1 / 3 » A 3D prototyping chip based on a wafer-level stacking techno... |
ASPDAC
2009
ACM
13 years 2 months ago
2009
ACM
We have developed a new 3-dimensional stacking technology using wafer-to-wafer stacked method and evaluated the connectivity between TSV and micro-bump. The prototype 3-layer stac...
ISCAS
2006
IEEE
2006
IEEE
Microelectromechanical systems in 3D SOI-CMOS: sensing electronics embedded in mechanical structures
13 years 10 months ago
— We discuss the design of CMOS MEMS in a 3D SOI-CMOS technology. We present layout architectures, preliminary mechanics modeling using finite element analysis and release proce...
NANONET
2009
Springer
13 years 9 months ago
2009
Springer
3D stacked chips have become a promising integration technology for modern systems. The complexity reached in multi-processor systems has increased the communication delays between...
TPDS
2010
13 years 3 months ago
2010
Abstract—A rising horizon in chip fabrication is the 3D integration technology. It stacks two or more dies vertically with a dense, highspeed interface to increase the device den...
ICPP
2008
IEEE
13 years 11 months ago
2008
IEEE
A rising horizon in chip fabrication is the 3D integration technology. It stacks two or more dies vertically with a dense, high-speed interface to increase the device density and ...