14 search results - page 2 / 3 » A BIST Structure to Test Delay Faults in a Scan Environment |
ITC
2003
IEEE
13 years 10 months ago
2003
IEEE
In a scan-based system with a large number of flip-flops, a major component of power is consumed during scanshift and clocking operation in test mode. In this paper, a novel scan-...
ITC
2003
IEEE
13 years 10 months ago
2003
IEEE
Diagnosing failing vectors in a Built-In Self Test (BIST) environment is a difficult task because of the highly compressed signature coming out of the Multiple Input Shift Regist...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
In this paper we describe how we applied a BIST-based approach to the test of a logic core to be included in System-on-achip (SoC) environments. The approach advantages are the ab...
ITC
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper deals with Hybrid multisite testing of VLSI chips by utilizing automatic test equipment (ATE) in connection with built-in self-test (BIST). The performance of a multisi...
ASPDAC
2005
ACM
13 years 7 months ago
2005
ACM
Recent research results have shown that the traditional structural testing for delay and crosstalk faults may result in over-testing due to the non-trivial number of such faults t...