22 search results - page 3 / 5 » A CS unplugged design pattern |
GECCO
2006
Springer
13 years 9 months ago
2006
Springer
Various methods for ensemble selection and classifier combination have been designed to optimize the results of ensembles of classifiers. Genetic algorithm (GA) which uses the div...
ISCAS
2005
IEEE
13 years 11 months ago
2005
IEEE
Abstract — Mapping applications onto different networks-onchip (NoCs) topologies is done by mapping processing cores on local ports of routers considering requirements like laten...
DAC
2006
ACM
14 years 6 months ago
2006
ACM
Networks-on-Chip (NoC) architectures provide a scalable solution to on-chip communication problem but the bandwidth offered by NoCs can be utilized efficiently only in presence of...
NOCS
2008
IEEE
14 years 4 days ago
2008
IEEE
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
MTDT
2003
IEEE
13 years 11 months ago
2003
IEEE
ct Defect-based testing for digital logic concentrates primarily on methods of test application, including for example at-speed structural tests and IDDQ testing. In contrast, defe...