15 search results - page 3 / 3 » A Clocked, Static Circuit Technique for Building Efficient H... |
DAC
2007
ACM
14 years 6 months ago
2007
ACM
Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability challenges in nano-scale technology. This paper presents an efficient technique to characte...
MICRO
2003
IEEE
13 years 11 months ago
2003
IEEE
Energy-efficient processor design is becoming more and more important with technology scaling and with high performance requirements. Supply-voltage scaling is an efficient way to...
GLVLSI
2006
IEEE
13 years 12 months ago
2006
IEEE
This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as c...
VISUALIZATION
1998
IEEE
13 years 10 months ago
1998
IEEE
Many sophisticated solutions have been proposed to reduce the geometric complexity of 3D meshes. A less studied problem is how to preserve on a simplified mesh the detail (e.g. co...
DAC
2003
ACM
14 years 6 months ago
2003
ACM
Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs offer the best pow...