2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology

This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as compared to conventional SerDes Designs, making it very attractive for modest budget multi-core and multi-processor ASICs with wide communication buses that are difficult to accommodate within the pin count of commonly available packaging. The design employs a “Statistical Random Sampling Technique” to observe and adjust the synchronization and serialization signals at start up rather than using a resource-heavy PLL or DLL based frequency multiplier/synthesizer and clock data recovery circuits. The serialization and deserialization logic is based on standard cell technology that makes the design highly portable. Multiple serial lines are bundled with a strobe that is used as a reference signal for deserialization. Data-to-strobe timing skew is compensated by adjusting the launch times of strobe and data sy...

• Type: Conference
• Year: 2006
• Where: GLVLSI
• Authors: Rashed Zafar Bhatti, Monty Denneau, Jeff Draper
• Keywords: Cell Based Design, Design, GLVLSI 2006, Standard Cell, VLSI