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EUROMICRO
2000
IEEE
13 years 10 months ago
A Simulink(c)-Based Approach to System Level Design and Architecture Selection
We propose a design flow for low-power and low-cost, data-dominated, embedded systems which tightly integrate different technologies and architectures. We use Mathworks’ Simuli...
Luciano Lavagno, Begoña Pino, Leonardo Mari...
RSP
2006
IEEE
102views Control Systems» more  RSP 2006»
13 years 11 months ago
Rapid Resource-Constrained Hardware Performance Estimation
In a hardware-software co-design environment, an application is partitioned into modules. Each module is then mapped either to software or to hardware. The mapping process is driv...
Basant Kumar Dwivedi, Arun Kejariwal, M. Balakrish...
LCPC
2005
Springer
13 years 11 months ago
Software Thread Level Speculation for the Java Language and Virtual Machine Environment
Thread level speculation (TLS) has shown great promise as a strategy for fine to medium grain automatic parallelisation, and in a hardware context techniques to ensure correct TLS...
Christopher J. F. Pickett, Clark Verbrugge
DATE
2005
IEEE
154views Hardware» more  DATE 2005»
13 years 11 months ago
A Time Slice Based Scheduler Model for System Level Design
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
Luciano Lavagno, Claudio Passerone, Vishal Shah, Y...
CODES
2009
IEEE
14 years 9 days ago
Using binary translation in event driven simulation for fast and flexible MPSoC simulation
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
Marius Gligor, Nicolas Fournel, Frédé...