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HPCA
2009
IEEE
14 years 6 months ago
Express Cube Topologies for on-Chip Interconnects
Driven by continuing scaling of Moore's law, chip multiprocessors and systems-on-a-chip are expected to grow the core count from dozens today to hundreds in the near future. ...
Boris Grot, Joel Hestness, Stephen W. Keckler, Onu...
GLOBECOM
2009
IEEE
13 years 9 months ago
On-Chip Integrated Antenna Structures in CMOS for 60 GHz WPAN Systems
Abstract--This paper presents several on-chip antenna structures that may be fabricated with standard CMOS technology for use at millimeter wave frequencies. On-chip antennas for w...
Felix Gutierrez Jr., Kristen Parrish, Theodore S. ...
TCAD
2010
124views more  TCAD 2010»
13 years 14 days ago
A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms
Abstract--This paper presents a GALS-compatible circuitswitched on-chip network that is well suited for use in many-core platforms targeting streaming DSP and embedded applications...
Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas
ICCAD
2003
IEEE
123views Hardware» more  ICCAD 2003»
14 years 2 months ago
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology
The Y-architecture for on-chip interconnect is based on pervasive use of 0-, 120-, and 240-degree oriented semi-global and global wiring. Its use of three uniform directions explo...
Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Io...
TPDS
2010
109views more  TPDS 2010»
13 years 4 months ago
Minimal Sets of Turns for Breaking Cycles in Graphs Modeling Networks
Abstract—We propose an algorithm that provides for deadlockfree and livelock-free routing, in particular in wormhole routed networks. The proposed algorithm requires nearly minim...
Lev B. Levitin, Mark G. Karpovsky, Mehmet Mustafa