3 search results - page 1 / 1 » A Compile-Time Partitioning Strategy for Non-Rectangular Loo... |
IPPS
1997
IEEE
13 years 9 months ago
1997
IEEE
This paper presents a compile-time scheme for partitioning non-rectangular loop nests which consist of inner loops whose bounds depend on the index of the outermost, parallel loop...
CASES
2008
ACM
13 years 6 months ago
2008
ACM
We present a novel loop transformation technique, particularly well suited for optimizing embedded compilers, where an increase in compilation time is acceptable in exchange for s...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
— Memory-intensive applications present unique challenges to an ASIC designer in terms of the choice of memory organization, memory size requirements, bandwidth and access latenc...