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TVLSI
2008
187views more  TVLSI 2008»
13 years 4 months ago
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
During the last years, the growing application complexity, design, and mask costs have compelled embedded system designers to increasingly consider partially reconfigurable applica...
Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Che...
IEEECIT
2010
IEEE
13 years 3 months ago
CFCSS without Aliasing for SPARC Architecture
With the increasing popularity of COTS (commercial off the shelf) components and multi-core processor in space and aviation applications, software fault tolerance becomes attracti...
Chao Wang, Zhongchuan Fu, Hongsong Chen, Wei Ba, B...
MICRO
2010
IEEE
156views Hardware» more  MICRO 2010»
13 years 3 months ago
Explicit Communication and Synchronization in SARC
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
Manolis Katevenis, Vassilis Papaefstathiou, Stamat...
NLE
2010
166views more  NLE 2010»
13 years 3 months ago
Wisdom of crowds versus wisdom of linguists - measuring the semantic relatedness of words
In this article, we present a comprehensive study aimed at computing semantic relatedness of word pairs. We analyze the performance of a large number of semantic relatedness measu...
Torsten Zesch, Iryna Gurevych
MST
2010
146views more  MST 2010»
12 years 11 months ago
The Cache-Oblivious Gaussian Elimination Paradigm: Theoretical Framework, Parallelization and Experimental Evaluation
We consider triply-nested loops of the type that occur in the standard Gaussian elimination algorithm, which we denote by GEP (or the Gaussian Elimination Paradigm). We present tw...
Rezaul Alam Chowdhury, Vijaya Ramachandran