29 search results - page 4 / 6 » A Configuration Memory Architecture for Fast Run-Time-Reconf... |
CATA
2009
13 years 6 months ago
2009
ABSTRACT: We present a Built-In Self-Test (BIST) approach for programmable embedded memories in Xilinx Virtex-4 Field Programmable Gate Arrays (FPGAs). The target resources are the...
FCCM
2005
IEEE
13 years 11 months ago
2005
IEEE
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
DATE
2008
IEEE
14 years 7 days ago
2008
IEEE
In this paper, we present an architecture exploration methodology for low-end embedded systems where the reduction of cost is a primary design concern. The architecture exploratio...
FPL
2000
Springer
13 years 9 months ago
2000
Springer
Abstract. This paper presents an innovative architecture for a reconfigurable device that allows single cycle context switching and single cycle random access to the unified on-chi...
NOCS
2007
IEEE
14 years 1 days ago
2007
IEEE
We present a novel network-on-chip-based architecture for future programmable chips (FPGAs). A key challenge for FPGA design is supporting numerous highly variable design instance...