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» A Decompression Architecture for Low Power Embedded Systems
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ICCD
2000
IEEE
94views Hardware» more  ICCD 2000»
13 years 9 months ago
A Decompression Architecture for Low Power Embedded Systems
Haris Lekatsas, Jörg Henkel, Wayne Wolf
DAC
2000
ACM
14 years 5 months ago
Code compression for low power embedded system design
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...
Haris Lekatsas, Jörg Henkel, Wayne Wolf
ISSS
1999
IEEE
131views Hardware» more  ISSS 1999»
13 years 9 months ago
Compressed Code Execution on DSP Architectures
Decreasing the program size has become an important goal in the design of embedded systems target to mass production. This problem has led to a number of efforts aimed at designin...
Paulo Centoducatte, Ricardo Pannain, Guido Araujo
IPPS
2007
IEEE
13 years 11 months ago
Code Compression and Decompression for Instruction Cell Based Reconfigurable Systems
Code compression has been applied to embedded systems to minimize the silicon area utilized for program memories, and lower the power consumption. More recently, it has become a n...
Nazish Aslam, Mark Milward, Ioannis Nousias, Tughr...
DATE
2003
IEEE
141views Hardware» more  DATE 2003»
13 years 10 months ago
On-chip Stack Based Memory Organization for Low Power Embedded Architectures
This paper presents a on-chip stack based memory organization that effectively reduces the energy dissipation in programmable embedded system architectures. Most embedded systems ...
Mahesh Mamidipaka, Nikil D. Dutt