59 search results - page 1 / 12 » A Delay Model and Speculative Architecture for Pipelined Rou... |
HPCA
2001
IEEE
14 years 5 months ago
2001
IEEE
This paper introduces a router delay model that accurately models key aspects of modern routers. The model accounts for the pipelined nature of contemporary routers, the specific ...
HPCA
2009
IEEE
14 years 6 months ago
2009
IEEE
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
FPGA
2003
ACM
13 years 10 months ago
2003
ACM
We present a pipelining-aware router for FPGAs. The problem of routing pipelined signals is different from the conventional FPGA routing problem. For example, the two terminal N-D...
DAC
2005
ACM
14 years 6 months ago
2005
ACM
The increased deployment of System-on-Chip designs has drawn attention to the limitations of on-chip interconnects. As a potential solution to these limitations, Networks-on -Chip...
MICRO
2003
IEEE
13 years 10 months ago
2003
IEEE
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...