Sciweavers

28 search results - page 6 / 6
» A Design Flow for Architecture Exploration and Implementatio...
Sort
View
TVLSI
2008
164views more  TVLSI 2008»
13 years 5 months ago
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...
ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
13 years 7 months ago
Translation caching: skip, don't walk (the page table)
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
Thomas W. Barr, Alan L. Cox, Scott Rixner
FCCM
2002
IEEE
156views VLSI» more  FCCM 2002»
13 years 10 months ago
MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64
The paper presents a Design Space Exploration (DSE) experiment which has been carried out in order to determine the optimum FPGA–based Variable-Length Decoder (VLD) computing re...
Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, ...