272 search results - page 3 / 55 » A Design Method for Heterogeneous Adders |
VLSI
2010
Springer
13 years 3 months ago
2010
Springer
—In this paper, we introduce a design methodology to implement low-complexity and high-speed digital Finite Impulse Response (FIR) filters. Since FIR filters suffer from a larg...
FPL
2009
Springer
13 years 10 months ago
2009
Springer
Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic b...
CAD
2004
Springer
13 years 5 months ago
2004
Springer
CAD
2005
Springer
13 years 5 months ago
2005
Springer
ARITH
1999
IEEE
13 years 9 months ago
1999
IEEE
The floating-point unit of a S/390 CMOS microprocessor is described. It contains a 116 bit fraction dataflow for addition and subtraction and a 64 bit-wide multiplier. Besides the...