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» A Family of Logical Fault Models for Reversible Circuits
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VTS
2003
IEEE
115views Hardware» more  VTS 2003»
13 years 10 months ago
Fault Testing for Reversible Circuits
Irreversible computation necessarily results in energy dissipation due to information loss. While small in comparison to the power consumption of today’s VLSI circuits, if curre...
Ketan N. Patel, John P. Hayes, Igor L. Markov
GLVLSI
2010
IEEE
209views VLSI» more  GLVLSI 2010»
13 years 10 months ago
Enhancing debugging of multiple missing control errors in reversible logic
Researchers are looking for alternatives to overcome the upcoming limits of conventional hardware technologies. Reversible logic thereby established itself as a promising directio...
Jean Christoph Jung, Stefan Frehse, Robert Wille, ...
DATE
2008
IEEE
121views Hardware» more  DATE 2008»
13 years 11 months ago
A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy
We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy, or more generally, a suboptimality in the synthe...
Irith Pomeranz, Sudhakar M. Reddy
CORR
2010
Springer
152views Education» more  CORR 2010»
13 years 2 months ago
Fault Tolerant Variable Block Carry Skip Logic (VBCSL) using Parity Preserving Reversible Gates
Reversible logic design has become one of the promising research directions in low power dissipating circuit design in the past few years and has found its application in low power...
Md. Saiful Islam 0003, Muhammad Mahbubur Rahman, Z...
VTS
2000
IEEE
84views Hardware» more  VTS 2000»
13 years 9 months ago
ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits
ESIM is a simulation tool that integrates logic fault and design error simulation for logic circuits. It targets several design error and fault models, and uses a novel mix of sim...
Hussain Al-Asaad, John P. Hayes