110 search results - page 2 / 22 » A Fast Hierarchical Algorithm for 3-D Capacitance Extraction |
DAC
2009
ACM
14 years 6 months ago
2009
ACM
State-of-the-art integral-equation-based solvers rely on techniques that can perform a matrix-vector multiplication in O(N) complexity. In this work, a fast inverse of linear comp...
ICCAD
1993
IEEE
13 years 9 months ago
1993
IEEE
For submicron integrated circuits, 3D numerical techniques are required to accurately compute the values of the interconnect capacitances. In this paper, we describe an hierarchic...
DAC
1996
ACM
13 years 9 months ago
1996
ACM
In order to optimize interconnect to avoid signal integrity problems, very fast and accurate 3-D capacitance extraction is essential. Fast algorithms, such as the multipole or prec...
ASPDAC
1999
ACM
13 years 9 months ago
1999
ACM
: In VLSI circuits with deep sub-micron, the parasitic capacitance from interconnect is a very important factor determining circuit performances such as power and time-delay. The B...
ICCAD
1996
IEEE
13 years 9 months ago
1996
IEEE
In this paper, we present a new capacitance extraction method named Dimension Reduction Technique (DRT) for 3D VLSI interconnects. The DRT converts a complex 3D problem into a ser...