98 search results - page 2 / 20 » A Formal Logic Approach to Constrained Combinatorial Testing |
FMCAD
2007
Springer
13 years 11 months ago
2007
Springer
— The concept of applying partial fencing to logic built-in self test (LBIST) hardware structures for the purpose of using partially good chips is well known in the chip design i...
ICRA
2007
IEEE
13 years 11 months ago
2007
IEEE
— Synthesis of robot behaviors towards nontrivial goals often requires reasoning about both discrete and continuous aspects of the underlying domain. Existing approaches in build...
DFT
2003
IEEE
13 years 10 months ago
2003
IEEE
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
IWANN
2009
Springer
13 years 11 months ago
2009
Springer
Generating test data for formal state based specifications is computationally expensive. This paper improves a framework that addresses this issue by representing the test data ge...
CAISE
2005
Springer
13 years 10 months ago
2005
Springer
Abstract. This paper uses a framework drawn from work in the philosophy of science to characterize the concepts of program correctness that have been used in software engineering, ...