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» A Genetic Testing Framework for Digital Integrated Circuits
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ASPDAC
2008
ACM
103views Hardware» more  ASPDAC 2008»
13 years 7 months ago
Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification
This paper presents an all digital measurement circuit called "gated oscillator" for capturing waveforms of dynamic power supply noise. The gated oscillator is constructe...
Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoy...
ISQED
2009
IEEE
112views Hardware» more  ISQED 2009»
14 years 4 days ago
Estimation and optimization of reliability of noisy digital circuits
— With continued scaling, reliability is emerging as a critical challenge for the designers of digital circuits. The challenge stems in part from the lack of computationally efï¬...
Satish Sivaswamy, Kia Bazargan, Marc D. Riedel
AIA
2007
13 years 6 months ago
Minimizing leakage: What if every gate could have its individual threshold voltage?
Designers aim at fast but low-power consuming integrated circuits. Since high processing speed always comes with high energy demands, the literature provides several ways to reduc...
Ralf Salomon, Frank Sill, Dirk Timmermann
ICCAD
2009
IEEE
144views Hardware» more  ICCAD 2009»
13 years 3 months ago
Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits
In this paper, we propose a new technique, referred to as virtual probe (VP), to efficiently measure, characterize and monitor both inter-die and spatially-correlated intra-die va...
Xin Li, Rob A. Rutenbar, R. D. (Shawn) Blanton
AHS
2006
IEEE
164views Hardware» more  AHS 2006»
13 years 11 months ago
Automatic Hybrid Genetic Algorithm Based Printed Circuit Board Inspection
The paper presents a novel integrated system in which a number of image processing algorithm are embedded within a Genetic Algorithm (GA) based framework in order to provide an ad...
Syamsiah Mashohor, Jonathan R. Evans, Ahmet T. Erd...