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ACL
1990
13 years 6 months ago
A Hardware Algorithm for High Speed Morpheme Extraction and its Implementation
This paper describes a new hardware algorithm for morpheme extraction and its implementation on a specific machine (MEX-I), as the first step toward achieving natural language par...
Toshikazu Fukushima, Yutaka Ohyama, Hitoshi Miyai
ISMB
1994
13 years 6 months ago
High Speed Pattern Matching in Genetic Data Base with Reconfigurable Hardware
Homologydetection in large data bases is probably the most time consuming operation in molecular genetic computing systems. Moreover, the progresses made all around the world conc...
Eric Lemoine, Joël Quinqueton, Jean Sallantin
DATE
2006
IEEE
85views Hardware» more  DATE 2006»
13 years 11 months ago
Optimizing high speed arithmetic circuits using three-term extraction
Carry Save Adder (CSA) trees are commonly used for high speed implementation of multi-operand additions. We present a method to reduce the number of the adders in CSA trees by ext...
Anup Hosangadi, Farzan Fallah, Ryan Kastner
FPL
2005
Springer
119views Hardware» more  FPL 2005»
13 years 11 months ago
Real-Time Feature Extraction for High Speed Networks
With the onset of Gigabit networks, current generation networking components will soon be insufficient for numerous reasons: most notably because existing methods cannot support h...
David Nguyen, Gokhan Memik, Seda Ogrenci Memik, Al...
GLVLSI
2005
IEEE
132views VLSI» more  GLVLSI 2005»
13 years 11 months ago
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
Abdallah Merhebi, Otmane Aït Mohamed