48 search results - page 10 / 10 » A Hardware Relaxation Paradigm for Solving NP-Hard Problems |
DAC
2005
ACM
14 years 5 months ago
2005
ACM
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
HPDC
1999
IEEE
13 years 9 months ago
1999
IEEE
We are developing a system for collaborative research and development for a distributed group of researchers at different institutions around the world. In a new paradigm for coll...
GLVLSI
1998
IEEE
13 years 9 months ago
1998
IEEE
In this research, we devised a new simple technique for statically holding analog weights, which does not require periodic refreshing. It further contains a mechanism to locally u...