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» A Heuristic for Clock Selection in High-Level Synthesis
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VLSID
2002
IEEE
105views VLSI» more  VLSID 2002»
12 years 6 months ago
A Heuristic for Clock Selection in High-Level Synthesis
Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or...
J. Ramanujam, Sandeep Deshpande, Jinpyo Hong, Mahm...
ISSS
1996
IEEE
94views Hardware» more  ISSS 1996»
11 years 10 months ago
Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification
Luca Benini, Patrick Vuillod, Claudionor Jos&eacut...
ASPDAC
2008
ACM
88views Hardware» more  ASPDAC 2008»
11 years 8 months ago
REWIRED - Register Write Inhibition by Resource Dedication
We propose REWIRED (REgister Write Inhibition by REsource Dedication), a technique for reducing power during high level synthesis (HLS) by selectively inhibiting the storage of fun...
Pushkar Tripathi, Rohan Jain, Srikanth Kurra, Pree...
ISLPED
2003
ACM
96views Hardware» more  ISLPED 2003»
11 years 11 months ago
Effective graph theoretic techniques for the generalized low power binding problem
This paper proposes two very fast graph theoretic heuristics for the low power binding problem given fixed number of resources and multiple architectures for the resources. First...
Azadeh Davoodi, Ankur Srivastava
FCCM
2011
IEEE
241views VLSI» more  FCCM 2011»
10 years 10 months ago
Multilevel Granularity Parallelism Synthesis on FPGAs
— Recent progress in High-Level Synthesis (HLS) es has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-genera...
Alexandros Papakonstantinou, Yun Liang, John A. St...
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