4 search results - page 1 / 1 » A High Speed VLSI Architecture for Scaleable ATM Switches |
GLVLSI
1996
IEEE
13 years 9 months ago
1996
IEEE
GLVLSI
2005
IEEE
13 years 10 months ago
2005
IEEE
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
VLSID
2001
IEEE
14 years 5 months ago
2001
IEEE
VLSID
2007
IEEE
14 years 5 months ago
2007
IEEE
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...