25 search results - page 1 / 5 » A High-Throughput Programmable Decoder for LDPC Convolutiona... |
ASAP
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper, we present and analyze a novel decoder architecture for LDPC convolutional codes (LDPCCCs). The proposed architecture enables high throughput and can be programmed ...
ISCAS
2008
IEEE
13 years 11 months ago
2008
IEEE
Abstract— We present the concepts and realization of a highly parallelized decoder architecture for LDPC convolutional codes and tailbiting LDPC convolutional codes. This archite...
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
Abstract— We analyze the decoding algorithm for regular timeinvariant LDPC convolutional codes as a 3D signal processing scheme and derive several parallelization concepts, which...
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
Abstract— A low-density parity-check (LDPC) decoder architecture that supports variable block sizes and multiple code rates is presented. The proposed architecture is based on th...
ASAP
2006
IEEE
13 years 8 months ago
2006
IEEE
Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates. This paper pr...