22 search results - page 2 / 5 » A Low Power 2-D DCT Chip Design Using Direct 2-D Algorithm |
DATE
2006
IEEE
13 years 10 months ago
2006
IEEE
We present a dynamic bit-width adaptation scheme in DCT applications for efficient trade-off between image quality and computation energy. Based on sensitivity differences of 64 ...
ESTIMEDIA
2005
Springer
13 years 10 months ago
2005
Springer
Designing Application-Specific Instruction-set Processors (ASIPs) usually requires designing a custom datapath, and modifying instruction-set, instruction decoder, and compiler. A...
TIP
1998
13 years 4 months ago
1998
—We propose novel discrete cosine transform (DCT) pseudophase techniques to estimate shift/delay between two onedimensional (1-D) signals directly from their DCT coefficients by...
ASPDAC
2009
ACM
13 years 9 months ago
2009
ACM
— In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in two-dimensional (2D) designs. Therefore, the power supply noise pro...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
- The use of reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such cores are being used for their flexibility, powerful functionality and low ...