19 search results - page 1 / 4 » A Mask Reuse Methodology for Reducing System-on-a-Chip Cost |
ISQED
2005
IEEE
13 years 10 months ago
2005
IEEE
Today's System-on-a-Chip (SoC) design methodology provides an efficient way to develop highly integrated systems on a single chip by utilizing pre-designed intellectual prope...
DFT
2003
IEEE
13 years 10 months ago
2003
IEEE
A new methodology for designing logic circuits with partial error masking is described. The key idea is to exploit the asymmetric soft error susceptibility of nodes in a logic cir...
ISQED
2011
IEEE
12 years 8 months ago
2011
IEEE
Due to the dramatic increase in design complexity, verifying the functional correctness of a circuit is becoming more difficult. Therefore, bugs may escape all verification effo...
DFT
2003
IEEE
13 years 10 months ago
2003
IEEE
We discuss the use of convolutional codes to perform concurrent error detection (CED) in finite state machines (FSMs). We examine a previously proposed methodology, we identify i...
DAC
1997
ACM
13 years 9 months ago
1997
ACM
A methodology for architecture exploration of look-up table based decoders is presented. For the degree of parallel processing a trade-off can be made by exploring system level an...