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» A Method to Reduce the Effect of the Switching Noise in Anal...
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ICCD
2006
IEEE
137views Hardware» more  ICCD 2006»
14 years 2 months ago
Reduction of Crosstalk Pessimism using Tendency Graph Approach
— Accurate estimation of worst-case crosstalk effects is critical for a realistic estimation of the worst-case behavior of deep sub-micron circuits. Crosstalk analysis models usu...
Murthy Palla, Klaus Koch, Jens Bargfrede, Manfred ...
ISLPED
1997
ACM
124views Hardware» more  ISLPED 1997»
13 years 9 months ago
Low power high level synthesis by increasing data correlation
With the increasing performance and density of VLSI circuits as well as the popularity of portable devices such as personal digital assistance, power consumption has emerged as an...
Dongwan Shin, Kiyoung Choi
ISCAS
2007
IEEE
120views Hardware» more  ISCAS 2007»
13 years 11 months ago
Clock Gating and Negative Edge Triggering for Energy Recovery Clock
Energy recovery clocking has been demonstrated as an effective method for reducing the clock power. In this method the conventional square wave clock signal is replaced by a sinus...
Vishwanadh Tirumalashetty, Hamid Mahmoodi
ICCAD
2007
IEEE
105views Hardware» more  ICCAD 2007»
13 years 11 months ago
Victim alignment in crosstalk aware timing analysis
Modeling the effect of coupling noise on circuit delay is a key issue in static timing analysis (STA) and involves the “victimaggressor alignment” problem. As delay-noise depe...
Ravikishore Gandikota, Kaviraj Chopra, David Blaau...
ISCAS
2005
IEEE
191views Hardware» more  ISCAS 2005»
13 years 11 months ago
Behavioural modeling and simulation of a switched-current phase locked loop
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...
Peter R. Wilson, Reuben Wilcock