12 search results - page 1 / 3 » A Model for Hardware Realization of Kernel Loops |
FPL
2003
Springer
13 years 10 months ago
2003
Springer
Abstract. Hardware realization of kernel loops holds the promise of accelerating the overall application performance and is therefore an important part of the synthesis process. In...
IMCSIT
2010
13 years 2 months ago
2010
The deployment of IEC61850 standard in the world of substation automation system brings to the use of specific strategies for architecture testing. To validate IEC61850 architectur...
IEEECIT
2010
IEEE
13 years 3 months ago
2010
IEEE
—As the need for embedded systems to interact with other systems is growing fast, we see great opportunities in introducing the hardware-in-the-loop technique to the field of ha...
CODES
2006
IEEE
13 years 11 months ago
2006
IEEE
In this paper, we present a methodology for designing a pipeline of accelerators for an application. The application is modeled using sequential C language with simple stylization...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
Reconfigurable Architectures are good candidates for application accelerators that cannot be set in stone at production time. FPGAs however, often suffer from the area and perfor...