Sciweavers

34 search results - page 1 / 7
» A Modular Memory BIST for Optimized Memory Repair
Sort
View
IOLTS
2008
IEEE
112views Hardware» more  IOLTS 2008»
13 years 11 months ago
A Modular Memory BIST for Optimized Memory Repair
An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. Most of the existing built-in self-repair solutions reuse IP-C...
Philipp Öhler, Alberto Bosio, Giorgio Di Nata...
ITC
2003
IEEE
116views Hardware» more  ITC 2003»
13 years 10 months ago
BIST for Deep Submicron ASIC Memories with High Performance Application
Today’s ASIC designs consist of more memory in terms of both area and number of instances. The shrinking of geometries has an even greater effect upon memories due to their tigh...
Theo J. Powell, Wu-Tung Cheng, Joseph Rayhawk, Ome...
MTDT
2003
IEEE
105views Hardware» more  MTDT 2003»
13 years 10 months ago
A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be ...
Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu L...
ITC
2003
IEEE
168views Hardware» more  ITC 2003»
13 years 10 months ago
A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy
Embedded memories are among the most widely used cores in current system-on-chip (SOC) implementations. Memory cores usually occupy a significant portion of the chip area, and do...
Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen ...
DATE
2003
IEEE
145views Hardware» more  DATE 2003»
13 years 10 months ago
Optimal Reconfiguration Functions for Column or Data-bit Built-In Self-Repair
In modern SoCs, embedded memories occupy the largest part of the chip area and include an even larger amount of active devices. As memories are designed very tightly to the limits...
Michael Nicolaidis, Nadir Achouri, Slimane Boutobz...