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TVLSI
2008
176views more  TVLSI 2008»
13 years 5 months ago
A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing
Abstract--Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact ...
Venkataraman Mahalingam, N. Ranganathan, J. E. Har...
ICCAD
2008
IEEE
106views Hardware» more  ICCAD 2008»
14 years 2 months ago
Process variability-aware transient fault modeling and analysis
– Due to reduction in device feature size and supply voltage, the sensitivity of digital systems to transient faults is increasing dramatically. As technology scales further, the...
Natasa Miskov-Zivanov, Kai-Chiang Wu, Diana Marcul...
ISLPED
2009
ACM
127views Hardware» more  ISLPED 2009»
14 years 2 days ago
Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic
In this paper, we observe that minimum energy Emin of subthreshold logic dramatically increases when reaching 45 nm node. We demonstrate by circuit simulation and analytical model...
David Bol, Dina Kamel, Denis Flandre, Jean-Didier ...
EURODAC
1994
IEEE
211views VHDL» more  EURODAC 1994»
13 years 9 months ago
Advanced simulation and modeling techniques for hardware quality verification of digital systems
synchronisation also play a fundamental role in overall system robustness. ElectroMagnetic Compatibility (EMC) and ElectroMagnetic Interference (EMI) issues also have to be conside...
S. Forno, Stephen Rochel
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
13 years 10 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...