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DATE
2008
IEEE
118views Hardware» more  DATE 2008»
13 years 6 months ago
Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices
Advanced MOSFETs such as Strained Silicon (SS) devices have emerged as critical enablers to keep Moore's law on track for sub100nm technologies. Use of Strained Silicon devic...
Ashutosh Chakraborty, Sean X. Shi, David Z. Pan
ICCAD
2003
IEEE
145views Hardware» more  ICCAD 2003»
14 years 1 months ago
Manufacturing-Aware Physical Design
Ultra-deep submicron manufacturability impacts physical design (PD) through complex layout rules and large guardbands for process variability; this creates new requirements for ne...
Puneet Gupta, Andrew B. Kahng
ICCAD
2007
IEEE
111views Hardware» more  ICCAD 2007»
14 years 1 months ago
Exploiting STI stress for performance
— Starting at the 65nm node, stress engineering to improve performance of transistors has been a major industry focus. An intrinsic stress source – shallow trench isolation –...
Andrew B. Kahng, Puneet Sharma, Rasit Onur Topalog...
BMCBI
2010
147views more  BMCBI 2010»
13 years 4 months ago
Learning biological network using mutual information and conditional independence
Background: Biological networks offer us a new way to investigate the interactions among different components and address the biological system as a whole. In this paper, a revers...
Dong-Chul Kim, Xiaoyu Wang, Chin-Rang Yang, Jean G...