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DATE
2000
IEEE
86views Hardware» more  DATE 2000»
13 years 9 months ago
A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level
Simulation is still one of the most important subtasks when designing a VLSI circuit. However, more and more elements on a chip increase simulation runtimes. Especially on transis...
Norbert Fröhlich, Volker Gloeckel, Josef Flei...
EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
13 years 9 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
ISLPED
2009
ACM
168views Hardware» more  ISLPED 2009»
13 years 11 months ago
Low power circuit design based on heterojunction tunneling transistors (HETTs)
The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low ...
Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, ...
FMCAD
2007
Springer
13 years 8 months ago
Circuit Level Verification of a High-Speed Toggle
As VLSI fabrication technology progresses to 65nm feature sizes and smaller, transistors no longer operate as ideal switches. This motivates verifying digital circuits using contin...
Chao Yan, Mark R. Greenstreet
DATE
2008
IEEE
102views Hardware» more  DATE 2008»
13 years 11 months ago
A New Approach for Combining Yield and Performance in Behavioural Models for Analogue Integrated Circuits
A new algorithm is presented that combines performance and variation objectives in a behavioural model for a given analogue circuit topology and process. The tradeoffs between per...
Sawal Ali, Reuben Wilcock, Peter R. Wilson, Andrew...