73 search results - page 1 / 15 » A New Pipelined Array Architecture for Signed Multiplication |
SBCCI
2003
ACM
13 years 10 months ago
2003
ACM
– We present a new architecture for signed multiplication which maintains the pure form of an array multiplier, exhibiting a much lower overhead than the Booth architecture. This...
FPL
2006
Springer
13 years 8 months ago
2006
Springer
A field-programmable gate array (FPGA) implementation of a new detection algorithm for uncoded multiple inputmultiple output (MIMO) systems based on the complex version of the sph...
ISCAS
2002
IEEE
13 years 10 months ago
2002
IEEE
In this paper, we focus on developing a new relaxed Givens rotations (RGR)-RLS algorithm and the corresponding RGR-RLS systolic array. The resulting algorithm and architecture pos...
DAC
2003
ACM
14 years 5 months ago
2003
ACM
In this paper, we describe a set of compiler analyses and an implementation that automatically map a sequential and un-annotated C program into a pipelined implementation, targete...
GLVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
Power-awareness indicates the scalability of the system energy with changing conditions and quality requirements. Multipliers are essential elements used in DSP applications and c...