45 search results - page 1 / 9 » A New System Design Methodology for Wire Pipelined SoC |
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
Wire Pipelining (WP) has been proposed in order to limit the impact of increasing wire delays. In general, the added pipeline elements alters the system such that architectural ch...
ICAC
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper proposes autonomic or organic computing principles to be applied to hardware design methods for future SoC solutions. Incorporating self-calibration, fault tolerance or...
ERSA
2006
13 years 6 months ago
2006
Reconfigurable devices, such as FPGAs, introduce into the design workflow of embedded systems a new degree of freedom: the designer can have the system autonomously modify the fun...
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
Inter-wire coupling is a major source of power consumption and delay faults for on-chip buses implemented in UDSM SoC Systems. Elimination or minimization of such faults is crucia...
ISSS
2002
IEEE
13 years 9 months ago
2002
IEEE
In this paper, we present a new methodology for application specific multiprocessor system-on-chip design. This approach facilitates the integration of existing components with th...