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» A Non-binary Parallel Arithmetic Architecture
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ESANN
2006
13 years 6 months ago
Parallel hardware implementation of a broad class of spiking neurons using serial arithmetic
Abstract. Current digital, directly mapped implementations of spiking neural networks use serial processing and parallel arithmetic. On a standard CPU, this might be the good choic...
Benjamin Schrauwen, Jan M. Van Campenhout
ASAP
2008
IEEE
119views Hardware» more  ASAP 2008»
13 years 7 months ago
An FPGA architecture for CABAC decoding in manycore systems
Arithmetic coding is an efficient entropy compression method that achieves results close to the entropy limit and it is used in modern standards such as JPEG-2000 and H.264. Arith...
Roberto R. Osorio, Javier D. Bruguera
ICIP
2009
IEEE
14 years 6 months ago
Architecture Design Of A High-performance Dual-symbol Binary Arithmetic Coder For Jpeg2000
The embedded-block coding with optimized truncation (EBCOT), which consists of a bit-plane coder (BPC) and a binary arithmetic coder (BAC), is the bottleneck in realizing a high-p...
PC
2002
158views Management» more  PC 2002»
13 years 5 months ago
On parallel block algorithms for exact triangularizations
We present a new parallel algorithm to compute an exact triangularization of large square or rectangular and dense or sparse matrices in any field. Using fast matrix multiplicatio...
Jean-Guillaume Dumas, Jean-Louis Roch
DSD
2003
IEEE
69views Hardware» more  DSD 2003»
13 years 10 months ago
A VLIW Architecture for Logarithmic Arithmetic
The Logarithmic Number System (LNS) is an alternative to IEEE-754 standard floating-point arithmetic. LNS multiply, divide and square root are easier than IEEE-754 and naturally ...
Mark G. Arnold