18 search results - page 3 / 4 » A Parallel Circuit-Partitioned Algorithm for Timing Driven C... |
DSRT
2008
IEEE
13 years 7 months ago
2008
IEEE
This paper proposes a novel Lightweight Time Warp (LTW) protocol for high-performance parallel optimistic simulation of large-scale DEVS and CellDEVS models. By exploiting the cha...
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
In this paper, we present an experimental integrated platform for the research, development and evaluation of new VLSI back-end algorithms and design flows. Interconnect scaling ...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
System-on-chip and system-in-package result in increased number of I/O cells and complicated constraints for both chip designs and package designs. This renders the traditional ma...
ARITH
1999
IEEE
13 years 9 months ago
1999
IEEE
The floating-point unit of a S/390 CMOS microprocessor is described. It contains a 116 bit fraction dataflow for addition and subtraction and a 64 bit-wide multiplier. Besides the...
VLSID
2002
IEEE
13 years 10 months ago
2002
IEEE
We propose a timing-oriented logic optimization technique called Generalized De Morgan (GDM) transform, that integrates gate resizing, net buffering and De Morgan transformation. ...