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EUROMICRO
1999
IEEE
13 years 10 months ago
Software Synthesis for System Level Design Using Process Execution Trees
Software synthesis for system level design languages becomes feasible because the current technology, pricing and application trends will most likely alleviate the industrial empha...
Leo J. van Bokhoven, Jeroen Voeten, Marc Geilen
ASPDAC
2005
ACM
113views Hardware» more  ASPDAC 2005»
13 years 11 months ago
Scalable interprocedural register allocation for high level synthesis
Abstract— The success of classical high level synthesis has been limited by the complexity of the applications it can handle, typically not large enough to necessitate the depart...
Rami Beidas, Jianwen Zhu
ASAP
2000
IEEE
125views Hardware» more  ASAP 2000»
13 years 10 months ago
High Level Modeling for Parallel Executions of Nested Loop Algorithms
High level modeling and (quantitative) performance analysis of signal processing systems requires high level models for the applications(algorithms) and the implementations (archi...
Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, B...
DAC
2007
ACM
14 years 6 months ago
Shared Resource Access Attributes for High-Level Contention Models
Emerging single-chip heterogeneous multiprocessors feature hundreds of design elements contending for shared resources, making it difficult to isolate performance impacts of indiv...
Alex Bobrek, JoAnn M. Paul, Donald E. Thomas
IPPS
1999
IEEE
13 years 10 months ago
Process Networks as a High-Level Notation for Metacomputing
Abstract. Our work involves the development of a prototype Geographical Information System GIS as an example of the use of process networks as a well-de ned high-level semantic mod...
Darren Webb, Andrew L. Wendelborn, Kevin Maciunas