30 search results - page 2 / 6 » A Placement Methodology for Robust Clocking |
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
—The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have st...
DAC
1994
ACM
13 years 9 months ago
1994
ACM
A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault co...
ISLPED
2010
ACM
13 years 5 months ago
2010
ACM
Structured ASICs provide an exciting middle ground between FPGA and ASIC design methodologies. Compared to ASIC, structured ASIC based designs require lower non recurring engineer...
ICCD
2004
IEEE
14 years 2 months ago
2004
IEEE
Abstract - This paper describes a communicationcentric design methodology that addresses the fundamental challenges induced by the emergence of truly heterogeneous Systems-on-Chip ...
DAC
1998
ACM
14 years 6 months ago
1998
ACM
Increasingly popular reuse-based design paradigms create a pressing need for authorship enforcement techniques that protect the intellectual property rights of designers. We devel...