14 search results - page 1 / 3 » A Practical Gate Resizing Technique Considering Glitch Reduc... |
DAC
1999
ACM
14 years 5 months ago
1999
ACM
We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only th...
DAC
2005
ACM
13 years 6 months ago
2005
ACM
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
AHS
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper, we present a low power implementation of H.264 adaptive deblocking filter (DBF) algorithm on ARM Versatile / PB926EJ-S Development Board. The DBF hardware is implem...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people oft...
ISQED
2006
IEEE
13 years 10 months ago
2006
IEEE
As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher perm...