11 search results - page 2 / 3 » A Probabilistic-Based Design Methodology for Nanoscale Compu... |
DAC
2005
ACM
14 years 6 months ago
2005
ACM
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
VLSID
2008
IEEE
14 years 5 months ago
2008
IEEE
Negative Bias Temperature Instability (NBTI) has been identified as a major and critical reliability issue for PMOS devices in nano-scale designs. It manifests as a negative thres...
ASAP
2005
IEEE
13 years 11 months ago
2005
IEEE
In this paper we introduce a design methodology that allows the system/circuit designer to build reliable systems out of unreliable nano-scale components. The central point of our...
DAC
2004
ACM
14 years 6 months ago
2004
ACM
Long design cycles due to the inability to predict silicon realities is a well-known problem that plagues analog/RF integrated circuit product development. As this problem worsens...
VLSID
2004
IEEE
14 years 5 months ago
2004
IEEE
As we move from deep submicron technology to nanotechnology for device manufacture, the need for defect-tolerant architectures is gaining importance. This is because, at the nanos...