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» A Quality-Driven Design Approach for NoCs
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DATE
2007
IEEE
173views Hardware» more  DATE 2007»
14 years 3 days ago
Analytical router modeling for networks-on-chip performance analysis
Networks-on-Chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largel...
Ümit Y. Ogras, Radu Marculescu
DAC
2009
ACM
14 years 6 months ago
NoC topology synthesis for supporting shutdown of voltage islands in SoCs
In many Systems on Chips (SoCs), the cores are clustered in to voltage islands. When cores in an island are unused, the entire island can be shutdown to reduce the leakage power c...
Ciprian Seiculescu, Srinivasan Murali, Luca Benini...
DATE
2006
IEEE
104views Hardware» more  DATE 2006»
13 years 11 months ago
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Increasing miniaturization is posing multiple challenges to electronic designers. In the context of Multi-Processor System-onChips (MPSoCs), we focus on the problem of implementin...
Federico Angiolini, Paolo Meloni, Salvatore Carta,...
ENTCS
2008
83views more  ENTCS 2008»
13 years 5 months ago
Elastic Flow in an Application Specific Network-on-Chip
A Network-on-Chip (NoC) is increasingly needed to interconnect the large number and variety of Intellectual Property (IP) cells that make up a System-on-Chip (SoC). The network mu...
Daniel Gebhardt, Kenneth S. Stevens
DATE
2009
IEEE
183views Hardware» more  DATE 2009»
14 years 16 days ago
SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips
Three-dimensional integrated circuits are a promising approach to address the integration challenges faced by current Systems on Chips (SoCs). Designing an efficient Network on C...
Ciprian Seiculescu, Srinivasan Murali, Luca Benini...