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DATE
2008
IEEE
110views Hardware» more  DATE 2008»
13 years 11 months ago
Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set
One of the upcoming challenges in embedded processing is to incorporate an increasing amount of adaptivity in order to respond to the multifarious constraints induced by today’s...
Lars Bauer, Muhammad Shafique, Stephanie Kreutz, J...
SAMOS
2009
Springer
13 years 11 months ago
Runtime Adaptive Extensible Embedded Processors - A Survey
Current generation embedded applications demand the computation engine to offer high performance similar to custom hardware circuits while preserving the flexibility of software s...
Huynh Phung Huynh, Tulika Mitra
ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
13 years 9 months ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for application−specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
IPPS
2006
IEEE
13 years 11 months ago
Dynamic configuration steering for a reconfigurable superscalar processor
A new dynamic vector approach for the selection and management of the configuration of a reconfigurable superscalar processor is proposed. This new method improves on previous wor...
Nick A. Mould, Brian F. Veale, Monte P. Tull, John...
APCSAC
2006
IEEE
13 years 11 months ago
Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays
Abstract. Bypass delays are expected to grow beyond 1ns as technology scales. These delays necessitate pipelining of bypass paths at processor frequencies above 1GHz and thus affe...
Lih Wen Koh, Oliver Diessel