89 search results - page 2 / 18 » A Statistical Gate-Delay Model Considering Intra-Gate Variab... |
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
DAC
2005
ACM
13 years 6 months ago
2005
ACM
Variability of process parameters makes prediction of digital circuit timing characteristics an important and challenging problem in modern chip design. Recently, statistical stat...
GLVLSI
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper approaches statistical optimization by examining gate delay variation models and optimization objectives. Most previous work on statistical optimization has focused exc...
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
Abstract— This paper presents an allocation method of decoupling capacitance that explicitly considers timing. We have found and focused that decap does not necessarily improve a...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing anal...