This paper presents a design methodology for a hybrid Hardwarein-the-Loop (HIL) tester tool, based on both discrete event system theory, given by timed automata, and continuous sy...
In this paper, the methodology for automated design of checker for communication protocol testing is presented. Based on the level of checking, different design strategies can be ...
In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemen...
Multi-FPGA systems (MFS's) represent a promising technology for various applications, such as the implementation of supercomputers and parallel and computational intensive emu...
Alessandro Panella, Marco D. Santambrogio, Frances...
This paper presents a methodology to design optimized electronic systems from high abstraction level descriptions. The methodology uses Genetic Programming in addition to high-leve...