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MAM
2008
138views more  MAM 2008»
13 years 5 months ago
FPGA based tester tool for hybrid real-time systems
This paper presents a design methodology for a hybrid Hardwarein-the-Loop (HIL) tester tool, based on both discrete event system theory, given by timed automata, and continuous sy...
Jan Krakora, Zdenek Hanzálek
DSD
2007
IEEE
119views Hardware» more  DSD 2007»
13 years 11 months ago
Online Protocol Testing for FPGA Based Fault Tolerant Systems
In this paper, the methodology for automated design of checker for communication protocol testing is presented. Based on the level of checking, different design strategies can be ...
Jiri Tobola, Zdenek Kotásek, Jan Korenek, T...
DFT
2007
IEEE
123views VLSI» more  DFT 2007»
13 years 11 months ago
Checker Design for On-line Testing of Xilinx FPGA Communication Protocols
In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemen...
Martin Straka, Jiri Tobola, Zdenek Kotásek
VLSI
2010
Springer
12 years 12 months ago
A design workflow for dynamically reconfigurable multi-FPGA systems
Multi-FPGA systems (MFS's) represent a promising technology for various applications, such as the implementation of supercomputers and parallel and computational intensive emu...
Alessandro Panella, Marco D. Santambrogio, Frances...
ICES
2003
Springer
151views Hardware» more  ICES 2003»
13 years 10 months ago
Using Genetic Programming and High Level Synthesis to Design Optimized Datapath
This paper presents a methodology to design optimized electronic systems from high abstraction level descriptions. The methodology uses Genetic Programming in addition to high-leve...
Sérgio G. Araújo, Antônio C. M...