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ISSS
2002
IEEE
148views Hardware» more  ISSS 2002»
13 years 10 months ago
A Case Study of Hardware and Software Synthesis in ForSyDe
ForSyDe (FORmal SYstem DEsign) is a methodology which addresses the design of SoC applications which may contain control as well as data flow dominated parts. Starting with a for...
Ingo Sander, Axel Jantsch, Zhonghai Lu
FPL
2005
Springer
140views Hardware» more  FPL 2005»
13 years 11 months ago
A Low-Energy FPGA: Architecture Design and Software-Supported Design Flow
The aim of the PhD thesis is the development of systematic methodologies both for hardware and software level for designing low-energy and performance efficient reconfigurable sys...
K. Siozios, Dimitrios Soudris, Adonios Thanailakis
DATE
2004
IEEE
136views Hardware» more  DATE 2004»
13 years 9 months ago
An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems
Recently a lot of multimedia applications are emerging on portable appliances. They require both the flexibility of upgradeable devices (traditionally software based) and a powerf...
Michele Borgatti, Andrea Capello, Umberto Rossi, J...
FPGA
2003
ACM
161views FPGA» more  FPGA 2003»
13 years 10 months ago
Implementation of BEE: a real-time large-scale hardware emulation engine
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, R...
FPL
2007
Springer
80views Hardware» more  FPL 2007»
13 years 11 months ago
A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems
A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize req...
Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi,...