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ATS
1998
IEEE
106views Hardware» more  ATS 1998»
13 years 9 months ago
A Test Pattern Generation Algorithm Exploiting Behavioral Information
This paper aims at broadening the scope of hierarchical ATPG to the behavioral-level The main problem of using behavioral information for ATPG is the mismatch of timing models bet...
Silvia Chiusano, Fulvio Corno, Paolo Prinetto
VTS
1999
IEEE
106views Hardware» more  VTS 1999»
13 years 9 months ago
RT-level TPG Exploiting High-Level Synthesis Information
High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test patte...
Silvia Chiusano, Fulvio Corno, Paolo Prinetto
FORTE
1998
13 years 6 months ago
Exploiting Symmetry in Protocol Testing
Test generation and execution are often hampered by the large state spaces of the systems involved. In automata (or transition system) based test algorithms, taking advantage of s...
Judi Romijn, Jan Springintveld
SAINT
2003
IEEE
13 years 10 months ago
Exploiting Pattern Relationship for Intrusion Detection
The problem of identifying patterns from system call trails of UNIX processes to better model application behavior has been investigated intensively. Most existing approaches focu...
Ning Jiang, Kien A. Hua, Jung-Hwan Oh
EURODAC
1994
IEEE
130views VHDL» more  EURODAC 1994»
13 years 9 months ago
RESIST: a recursive test pattern generation algorithm for path delay faults
This paper presents Resist, a recursive test pattern generation (TPG) algorithm for path delay fault testing of scan-based circuits. In contrast to other approaches, it exploits t...
Karl Fuchs, Michael Pabst, Torsten Rössel