70 search results - page 2 / 14 » A Test Pattern Generation Methodology for Low-Power Consumpt... |
IJON
2007
13 years 5 months ago
2007
— This paper, presents a feasability study of a central pattern generator-based analog controller for an autonomous robot. The operation of a neuronal circuit formed of electroni...
ATS
2000
IEEE
13 years 10 months ago
2000
IEEE
EUROGP
2001
Springer
13 years 10 months ago
2001
Springer
An evolutionary algorithm is used to design a finite impulse response digital filter with reduced power consumption. The proposed design approach combines genetic optimization an...
ICCD
2002
IEEE
14 years 2 months ago
2002
IEEE
Low power design techniques have been employed for more than two decades, however an emerging problem is satisfying the test power constraints for avoiding destructive test and im...
DFT
2005
IEEE
13 years 8 months ago
2005
IEEE
A built-in self-test (BIST) scheme is presented which both reduces overhead for detecting random-pattern-resistant (r.p.r.) faults as well as reduces power consumption during test...