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» A Time Predictable Instruction Cache for a Java Processor
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JSA
2008
142views more  JSA 2008»
13 years 4 months ago
A Java processor architecture for embedded real-time systems
Architectural advancements in modern processor designs increase average performance with features such as pipelines, caches, branch prediction, and out-of-order execution. However...
Martin Schoeberl
ASPLOS
2006
ACM
13 years 11 months ago
Software-based instruction caching for embedded processors
While hardware instruction caches are present in virtually all general-purpose and high-performance microprocessors today, many embedded processors use SRAM or scratchpad memories...
Jason E. Miller, Anant Agarwal
ISORC
2011
IEEE
12 years 8 months ago
A Time-Predictable Object Cache
—Static cache analysis for data allocated on the heap is practically impossible for standard data caches. We propose a distinct object cache for heap allocated data. The cache is...
Martin Schoeberl
DAC
2012
ACM
11 years 7 months ago
WCET-centric partial instruction cache locking
Caches play an important role in embedded systems by bridging the performance gap between high speed processors and slow memory. At the same time, caches introduce imprecision in ...
Huping Ding, Yun Liang, Tulika Mitra
RTS
2006
129views more  RTS 2006»
13 years 4 months ago
Modeling out-of-order processors for WCET analysis
Estimating the Worst Case Execution Time (WCET) of a program on a given processor is important for the schedulability analysis of real-time systems. WCET analysis techniques typic...
Xianfeng Li, Abhik Roychoudhury, Tulika Mitra